D.13 The Ravenscar ProfileRun-time Profiles
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AI95-00249-01}
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AI05-0246-1}
[This clause defines
the Ravenscar profile. specifies
a mechanism for defining run-time profiles. ]
Syntax
2/3
3/3
Legality Rules
4/3
Static Semantics
5/3
{
AI95-00249-01}
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AI05-0246-1}
The usage profile
Ravenscar is equivalent to the following set of pragmas: A
profile is equivalent to the set of configuration pragmas that is defined
for each run-time profile.
6/3
{
AI95-00249-01}
{
AI95-00297-01}
{
AI95-00394-01}
{
AI05-0171-1}
{
AI05-0246-1}
pragma Task_Dispatching_Policy (FIFO_Within_Priorities);
pragma Locking_Policy (Ceiling_Locking);
pragma Detect_Blocking;
pragma Restrictions (
No_Abort_Statements,
No_Dynamic_Attachment,
No_Dynamic_Priorities,
No_Implicit_Heap_Allocations,
No_Local_Protected_Objects,
No_Local_Timing_Events,
No_Protected_Type_Allocators,
No_Relative_Delay,
No_Requeue_Statements,
No_Select_Statements,
No_Specific_Termination_Handlers,
No_Task_Allocators,
No_Task_Hierarchy,
No_Task_Termination,
Simple_Barriers,
Max_Entry_Queue_Length => 1,
Max_Protected_Entries => 1,
Max_Task_Entries => 0,
No_Dependence => Ada.Asynchronous_Task_Control,
No_Dependence => Ada.Calendar,
No_Dependence => Ada.Execution_Time.Group_Budgets,
No_Dependence => Ada.Execution_Time.Timers,
No_Dependence => Ada.Task_Attributes,
No_Dependence => System.Multiprocessors.Dispatching_Domains);
6.a/3
Discussion: The
Ravenscar profile is named for the location of the meeting that defined
its initial version. The name is now in widespread use, so we stick with
existing practice, rather than using a more descriptive name.
Post-Compilation Rules
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Implementation Requirements
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AI05-0171-1}
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AI05-0229-1}
A task shall only be on the ready queues of one
processor, and the processor to which a task belongs shall be defined
statically. Whenever a task running on a processor reaches a task dispatching
point, it goes back to the ready queues of the same processor. A task
with a CPU value of Not_A_Specific_CPU will execute on an implementation
defined processor. [A task without a CPU aspect will activate and execute
on the same processor as its activating task.]
8.a/3
Proof: The processor
of a task without a aspect CPU is defined in D.16.
8.a.1/3
Implementation defined:
The processor on which a task with a
CPU value of a Not_A_Specific_CPU will execute when the Ravenscar profile
is in effect.
Implementation Advice
9/3
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AI05-0171-1}
On a multiprocessor system, an implementation should
support a fully partitioned approach. Each processor should have separate
and disjoint ready queues.
9.a.1/3
Implementation Advice:
On a multiprocessor system, each processor
should have a separate and disjoint ready queue.
10/3
46 {
AI95-00249-01}
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AI05-0246-1}
The effect of the Max_Entry_Queue_Length =>
1 restriction applies only to protected entry queues due to the accompanying
restriction of Max_Task_Entries => 0.
Extensions to Ada 95
10.a/3
Wording Changes from Ada 2005
10.b/3
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AI05-0171-1}
How Ravenscar behaves on a multiprocessor system
is now defined.
Ada 2005 and 2012 Editions sponsored in part by Ada-Europe